The present invention relates to a hybrid power MOSFET having a low blocking-capability MOSFET and a high blocking-capability junction FET.
A hybrid power MOSFET having a low blocking-capability MOSFET and a high blocking-capability junction FET is known from DE 196 10 135 C1. FIG. 1 is used herein to describe this known hybrid power MOSFET in more detail.
Referring to FIG. 1, this hybrid power MOSFET has a normally-off n-channel MOSFET 2, in particular a low voltage power MOSFET, and a normally-on n-channel junction FET 4. This high blocking-capability junction FET 4 is also referred to as a Junction Field Effect Transistor (JFET). These two FETs are electrically connected in series such that the source connection S of the junction FET 4 is electrically conductively connected to the drain connection Dxe2x80x2 of the MOSFET 2, and that the gate connection G of the junction FET 4 is electrically conductively connected to the source connection Sxe2x80x2 of the MOSFET 2. This electrical interconnection of these two semiconductor components is also commonly known as a cascode circuit. The low blocking-capability MOSFET 2 in this cascode circuit has an internal bipolar diode DIN which is connected in antiparallel with MOSFET 2 and is referred to generally as an inverse diode or internal freewheeling diode. The normally-off n-channel MOSFET 2 is made of silicon, whereas the normally-off n-channel JFET 4 is made of silicon carbide. This hybrid power MOSFET is designed for a high reverse voltage of over 600 volts and has only low losses in the passband.
This known cascode circuit is controlled using the gate voltage UGxe2x80x2Sxe2x80x2 of the normally-off MOSFET 2. If MOSFET 2 is on or the antiparallel internal diode DIN of MOSFET 2 is conducting a current, the drain voltage UDxe2x80x2Sxe2x80x2 of MOSFET 2 is approximately zero. The coupling between the gate connection of JFET 4 and the source connection Sxe2x80x2 of MOSFET 2 means that the gate voltage UGSxe2x80x2 of JFET 4 is zero to slightly negative or positive. In accordance with a transfer characteristic, approximately the largest drain current ID flows through JFET 4. If MOSFET 2 is turned off, the drain voltage UDxe2x80x2Sxe2x80x2 rises until the maximum permissible reverse voltage of MOSFET 2 has been reached. The value of the reverse voltage in a low voltage power MOSFET 2 is 30 volts, for example. As soon as the value of the drain voltage UDxe2x80x2Sxe2x80x2 of MOSFET 2 exceeds the value of the threshold voltage UTh of JFET 4, the drain current ID of JFET 4 is zero in accordance with its transfer characteristic. In other words JFET 4 is off. The coupling between the gate connection G of JFET 4 and the source connection Sxe2x80x2 of MOSFET 2 means that the drain voltage UDxe2x80x2Sxe2x80x2 of MOSFET 2 is fed back negatively to the gate G of JFET 4.
The known hybrid power MOSFET can, in principle, be connected in parallel, thereby increasing the current-carrying capacity of the whole arrangement. The drawbacks of such a conventional parallel connection of n cascode circuits are as follows: (a) with n parallel cascode circuits, 2n chips are required, which complicates the design technology; and (b) with n parallel cascode circuits, n control lines are required on account of the decoupling of the gate connections of the n MOSFETs.
The present invention provides for increasing the current-carrying capacity of the known hybrid power MOSFET by using only one low blocking-capability MOSFET and at least two high blocking-capability junction FETs electrically connected in parallel, thus reducing the number of chips in a hybrid power MOSFET having n high blocking-capability junction FETs to n+1 chips. In addition, only one control line is required, since only one low blocking-capability MOSFET is used. This MOSFET has the function of a control head. In addition, the design technology for this inventive hybrid power MOSFET for a high current-carrying capacity is greatly simplified, since instead of 2n chips in a conventional parallel circuit only n+1 chips are now used in the cascode circuit.
In one advantageous refinement of the inventive hybrid power MOSFET of the present invention, a gate resistor is arranged in each connecting line between a gate connection of the parallel-connected junction FETs and a source connection of the low blocking-capability MOSFET. This decouples the control loops of the junction FETs from one another and thus significantly improves the switching response of the hybrid power MOSFET.
In another advantageous refinement of the inventive hybrid power MOSFET of the present invention, an inductance is arranged in each connecting line between the drain connection of the low blocking-capability MOSFET and a source connection of the parallel-connected junction FETs. This improves the balancing of the dynamic current division of the hybrid power MOSFET.
In another advantageous refinement of the present invention, each junction FET of the inventive hybrid power MOSFET has a gate resistor, and a respective inductance is arranged in the connecting lines of the MOSFET with the parallel-connected junction FETs. Thus, a hybrid power MOSFET is obtained whose switching procedure and whose balancing of the dynamic current distribution has been improved. This embodiment is particularly advantageous when the inductance used is a respective elongated bonding wire.